Optical I/O Takes Center Stage at SC23
insideHPC, Tuesday, November 7,2023
HPC demands the greater throughput, lower latency, and improved power efficiency promised by in-package optical interconnects
Modern HPC (high performance computing) and AI (artificial intelligence) workloads are pushing the boundaries of current system architectures. Vendors continue to respond with ever-increasing performance for CPUs and GPUs, and platform designs that leverage parallel processing, packaging innovations (such as chiplet technology) and greater processor and memory density.
Unfortunately, banking on the future of HPC by deploying a large volume of processors - essentially, throwing chips at the problem - using existing interconnect solutions is a losing proposition. It creates massive I/O bottlenecks, limiting overall processor utilization as systems spend far more time waiting on data than processing it. This creates a race to the bottom: more processors are required to make up for the compute inefficiency, which further adds to bottlenecks while significantly increasing power consumption, along with CapEx and OpEx.