RISC-V Based Architecture Integrates Complex Memory Tasks to Processor
OpenSourceForU, Tuesday, January 30th, 2024
VyperCore, a UK-based startup located in Bristol, has achieved a significant milestone in the development of a new chip architecture that incorporates RISC-V. They have successfully demonstrated the RTL (Register-Transfer Level) design of this technology in a RISC-V processor simulation, executing code for the first time.
They plan to release a hardware version of this technology by June 2024.
The technology will improve efficiency by transferring complex memory-related tasks, such as Garbage Collection, from software to the silicon layer. This integration into the processor itself reduces the overhead of running these tasks in the background, allowing the CPU to focus more on running the user's application. During research, 7x acceleration in applications was observed.